module instruction_dec_tb();

reg err
reg [15:0] ireg; //from instruction register
reg [2:0] nsel;
reg [2:0] opcode, readnum, writenum;
reg [1:0] op, ALUop, shift;
reg [15:0] sximm5, sximm8;

instruction_dec DUT(ireg, nsel, opcode, op, ALUop, 
    sximm5, sximm8, shift, readnum, writenum);

task deccheck;
    input [15:0] expected_sximm5;
    input [15:0] expected_sximm8;
    input [2:0] expected_opcode;
    input [2:0] expected_readnum;
    input [2:0] expected_writenum;
    input [1:0] expected_op;
    input [1:0] expected_ALUop;
    input [1:0] expected_shift;
begin
    
    if(ALU_tb.DUT.sximm5 !== expected_sximm5) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.sximm5, expected_sximm5);
        err = 1'b1; end

    if(ALU_tb.DUT.sximm8 !== expected_sximm8) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.sximm8, expected_sximm8);
        err = 1'b1; end

    if(ALU_tb.DUT.opcode !== expected_opcode) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.opcode, expected_opcode);
        err = 1'b1; end

    if(ALU_tb.DUT.readnum !== expected_readnum) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.readnum, expected_readnum);
        err = 1'b1; end

    if(ALU_tb.DUT.writenum !== expected_writenum) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.writenum, expected_writenum);
        err = 1'b1; end

    if(ALU_tb.DUT.op !== expected_op) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.op, expected_op);
        err = 1'b1; end

    if(ALU_tb.DUT.ALUop !== expected_ALUop) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.ALUop, expected_ALUop);
        err = 1'b1; end

    if(ALU_tb.DUT.shift !== expected_shift) begin
        $display("ERROR: output is %b, expected %b",
        ALU_tb.DUT.shift, expected_shift);
        err = 1'b1; end
end
endtask

initial begin
    clk = 1'b0; #5;
    forever begin
        clk = 1'b1; #5;
        clk = 1'b0; #5;
    end
end

initial begin
    err = 1'b0;

    $display("Checking ...");
    ireg = 16'b0000000000000000;
    nsel = 3'b000; #10
    deccheck(16'b0000000000000000, 16'b0000000000000000,
        3'b000, 3'b000, 3'b000, 2'b00, 2'b00, 2'b00);

    if(~err) $display("PASSED");
    else $display("FAILED");
    $stop;

//Delay to reach 500 picoseconds

end
endmodule