module regfile_tb(); // add comments

  // i/o signals for register file 
  reg [15:0] data_in;  
  reg [2:0]  writenum;
  reg        write;
  reg [2:0]  readnum;
  reg        clk;
  wire [15:0] data_out;
  reg        err;
  wire [15:0] R0, R1, R2, R3, R4, R5, R6, R7;

regfile DUT(data_in, writenum, write, readnum, clk, data_out );

task mychecker;

  input [15:0] expected_data_out;


begin

if(regfile_tb.DUT.data_out !== expected_data_out) begin
  $display("ERROR ** data_out is %b, expected %b", 
  regfile_tb.DUT.data_out, expected_data_out);
  err = 1'b1; end



end
endtask


initial begin
    clk = 1'b0; #5;

forever begin
    clk = 1'b1; #5;
    clk = 1'b0; #5;
end
end

initial begin

  err = 1'b0;


  $display("checking data input 2 in register 3");
  write = 1'b1;
  writenum = 3'b011;
  data_in = 16'b0000000000000010;
  readnum = 3'b011;
  #10;
  mychecker(16'b0000000000000010);

  $display("checking data input 27 in register 5");
  write = 1'b1;
  writenum = 3'b101;
  data_in = 16'b0000000000011011; 
  readnum = 3'b101;
  #10;
  mychecker(16'b0000000000011011);

  $display("checking data input 228 in register 0");
  write = 1'b1;
  writenum = 3'b000;
  data_in = 16'b0000000011100100; 
  readnum = 3'b000;
  #10;
  mychecker(16'b0000000011100100);

  $display("checking data input 228 in different register than 0");
  write = 1'b1;
  writenum = 3'b000;
  data_in = 16'b0000000011100100; 
  readnum = 3'b001;
  #10;
  mychecker(16'bxxxxxxxxxxxxxxx);

  if(~err) $display("PASSED");
  else $display("FAILED");

#460;

$stop;

end
endmodule