/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* alu.v */

module ALU(Ain, Bin, ALUop, out, Z);
    
    //i/o signals for ALU   
    input [15:0] Ain, Bin;
    input [1:0] ALUop;
    output reg [15:0] out;
    output reg [2:0] Z;

    always @(*) begin //decides which ALU operation
        case(ALUop)
            2'b00: out = Ain + Bin; //add operation
            2'b01: out = Ain - Bin; //subtract operation
            2'b10: out = Ain & Bin; //and operation
            2'b11: out = ~Bin; //inverse operation
            default: out = {16{1'bX}};
        endcase
	
	    //zero flag
        if(out == {16{1'b0}})
            Z[0] = 1'b1;
        else
            Z[0] = 1'b0; //if out signal is not zero

        //overflow flag
        if(Ain[7] && Bin[7] !== Ain[6] && Bin[6])
            Z[1] = 1'b1;
        else
            Z[1] = 1'b0;

        //negative flag
        if(out[7] == 1'b1)
            Z[2] = 1'b1;
        else
            Z[2] = 1'b0;

    end
endmodule