/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* cpu.v */

module cpu(clk, reset, read_data, N, V, Z, write_data);
    
    //i/o signals
    input clk, reset;
    input [15:0] read_data;
    output N, V, Z;
    output [15:0] write_data;

    wire [15:0] ireg;
    wire [15:0] sximm5, sximm8;
    wire [8:0] PC;
    wire [2:0] writenum, readnum, nsel, opcode;
    wire [1:0] shift, ALUop, op, mem_cmd;
    wire write, load_ir, loada, loadb, loadc, loads, asel, bsel, reset_pc, load_pc, addr_sel, load_addr;
    wire [3:0] vsel;
    wire [8:0] pcout, muxPCin, dataaddrout, mem_addr;
    reg [8:0] next_pc;

always @(*) begin

  case(reset_pc)
  1'b1 : next_pc = 9'b000000000;
  1'b0 : next_pc = muxPCin;
  default : next_pc = 9'bxxxxxxxxx;
  endcase

end

vDFFE #(16) in_reg(clk, load_ir, read_data, ireg);
//vDFFE #(16) in_reg(.clk(clk), .load_ir(load_ir), .read_data(read_data), .out(ireg)); //instantiation for instruction register

instruction_dec in_dec(.ireg(ireg), .nsel(nsel), .opcode(opcode), .op(op), .ALUop(ALUop), .sximm5(sximm5), .sximm8(sximm8), .shift(shift), .readnum(readnum), .writenum(writenum)); //instantiation for instruction decoder


datapath DP(.sximm5(sximm5), .sximm8(sximm8), .read_data(read_data), .PC(PC), .writenum(writenum), .write(write), .readnum(readnum), .clk(clk),
                .loada(loada), .loadb(loadb), .loadc(loadc), .loads(loads), .vsel(vsel), .asel(asel), .bsel(bsel), 
                .shift(shift), .ALUop(ALUop), .Z_out({N,V,Z}), .write_data(write_data)); //instantiation for datapath

fsm_controller CTRL(.clk(clk), .reset(reset), .opcode(opcode), .op(op), .write(write),
    .loada(loada), .loadb(loadb), .loadc(loadc), .loads(loads), .asel(asel), .bsel(bsel), .vsel(vsel), .nsel(nsel),
    .reset_pc(reset_pc), .load_pc(load_pc), .mem_cmd(mem_cmd), .addr_sel(addr_sel), .load_ir(load_ir), .load_addr(load_addr)); //instantiation for fsm controller

adder #(9) add1(pcout, muxPCin); 

//Muxtop #(9) muxPC(muxPCin, 9'b000000000, reset_pc, next_pc); 

vDFFE #(9) PC1(clk, load_pc, next_pc, pcout);

//assign PC = {1'b0, pcout[7:0]};

vDFFE #(9) ADDR1(clk, load_addr, write_data[8:0], dataaddrout);

Muxtop #(9) muxADDR(dataaddrout, pcout, addr_sel, mem_addr);

endmodule