/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* datapath.v */

module datapath(sximm5, sximm8, read_data, PC, writenum, write, readnum, clk,
                loada, loadb, loadc, loads, vsel, asel, bsel, 
                shift, ALUop, Z_out, write_data);

    //i/o signals
    input [15:0] sximm5, sximm8, read_data;
    input [8:0] PC;
    input [2:0] writenum, readnum;
    input [1:0] shift, ALUop;
    input write, clk, loada, loadb, loadc, loads, asel, bsel;
    input [3:0] vsel;
    output [15:0] write_data; 
    output [2:0] Z_out;
    wire [15:0] zeros;
    assign zeros = 16'b0000000000000000;
    wire [15:0] data_out;
    wire [15:0] out, in, sout, muxoutA; 
    wire [2:0] Z;
    wire [15:0] Ain, Bin;
    reg [15:0] data_in;

    always @(*) begin //4 input Mux
        case(vsel) //determines use of new or old data
        4'b0001 : data_in = write_data;
        4'b0010 : data_in = read_data;
        4'b0100 : data_in = sximm8;
        4'b1000 : data_in = PC;
        default : data_in = {16{1'bx}};
        endcase
    end

    regfile REGFILE(.data_in(data_in), .writenum(writenum), .write(write), .readnum(readnum), .clk(clk), .data_out(data_out)); //call to regfile component to store data in registers and read from such registers

    vDFFE #(16) F1(.clk(clk), .load(loada), .in(data_out), .out(muxoutA)); //load enabled DFF to use either regfile output data or not allow new data
    vDFFE #(16) F2(.clk(clk), .load(loadb), .in(data_out), .out(in));

    shifter U1(.in(in), .shift(shift), .sout(sout)); //call to shift component to either not shift, shift left or right, or shift right with MSB maintained

    Mux2 #(16) M2(.in1(zeros), .in0(muxoutA), .sel(asel), .ALUin(Ain)); //multiplexer to decide whether to use datapath input or all zeros
    Mux2 #(16) M3(.in1(sximm5), .in0(sout), .sel(bsel), .ALUin(Bin)); //multiplexer to decide whether to use datapath input or zeros and 4 LSB of datapath input

    ALU U2(.Ain(Ain), .Bin(Bin), .ALUop(ALUop), .out(out), .Z(Z)); //call to ALU component to either add, subtract, or AND data, or inverse second datapath input

    vDFFE #(16) F3(.clk(clk), .load(loadc), .in(out), .out(write_data)); //load enabled DFF to use either modified datapath input or not allow new data
    vDFFE #(3) F4(.clk(clk), .load(loads), .in(Z), .out(Z_out)); //load enabled DFF to use either new Z output or not allow new data

endmodule

//2 input Mux
module Mux2(in1, in0, sel, ALUin);
    parameter k = 16;
    input [k-1:0] in1, in0;
    input sel;
    output reg [k-1:0] ALUin;

    always @(*) begin
        case(sel) //determines use of new or old data
        1'b1 : ALUin = in1;
        1'b0 : ALUin = in0;
        default : ALUin = {16{1'bx}};
        endcase
    end
endmodule