module fsm_controller_tb();

reg err, reset, s, clk;
reg [2:0] opcode;
reg [1:0] op;
reg write, loada, loadb, loadc, loads, asel, bsel, w; 
reg [3:0] vsel;
reg [2:0] nsel;

fsm_controller DUT(clk, reset, s, opcode, op, write,
    loada, loadb, loadc, loads, asel, bsel, vsel, nsel, w);

task fsmcheck;
    input [3:0] expected_vsel;
    input [2:0] expected_nsel;
    input expected_write;
    input expected_loada;
    input expected_loadb;
    input expected_loadc;
    input expected_loads;
    input expected_asel;
    input expected_bsel;
    input expected_w;
begin

    if(cpu_tb.DUT.vsel !== expected_vsel) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.vsel, expected_vsel);
        err = 1'b1; end

    if(cpu_tb.DUT.nsel !== expected_nsel) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.nsel, expected_nsel);
        err = 1'b1; end

    if(cpu_tb.DUT.write !== expected_write) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.write, expected_write);
        err = 1'b1; end
    
    if(cpu_tb.DUT.loada !== expected_loada) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.loada, expected_loada);
        err = 1'b1; end
    
    if(cpu_tb.DUT.loadb !== expected_loadb) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.loadb, expected_loadb);
        err = 1'b1; end
    
    if(cpu_tb.DUT.loadc !== expected_loadc) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.loadc, expected_loadc);
        err = 1'b1; end
    
    if(cpu_tb.DUT.loads !== expected_loads) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.loads, expected_loads);
        err = 1'b1; end
    
    if(cpu_tb.DUT.asel !== expected_asel) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.asel, expected_asel);
        err = 1'b1; end
    
    if(cpu_tb.DUT.bsel !== expected_bsel) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.bsel, expected_bsel);
        err = 1'b1; end

    if(cpu_tb.DUT.w !== expected_w) begin
        $display("ERROR: output is %b, expected %b",
        cpu_tb.DUT.w, expected_w);
        err = 1'b1; end
end
endtask

initial begin
    clk = 1'b0; #5;
    forever begin
        clk = 1'b1; #5;
        clk = 1'b0; #5;
    end
end

initial begin
    err = 1'b0;
    //RESET CHECK HERE

    $display("Checking ...");
    reset = 1'b0; s = 1'b1;
    opcode = 3'b000;
    op = 2'b00; #10
    fsmcheck(4'b0000, 3'b000, 1'b0, 1'b0, 1'b0,
         1'b0, 1'b0, 1'b0, 1'b0, 1'b0);

    if(~err) $display("PASSED");
    else $display("FAILED");
    $stop;

//Delay to reach for 500 picoseconds

end
endmodule