/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* instruction_dec.v */

module instruction_dec(ireg, nsel, opcode, op, ALUop, sximm5, sximm8, shift, readnum, writenum);

    //i/o signals
    input [15:0] ireg; //from instruction register
    input [2:0] nsel;
    output [2:0] opcode, readnum, writenum;
    output [1:0] op, ALUop, shift;
    output reg [15:0] sximm5, sximm8;
    
    //reg wires
    reg [2:0] opcode, Rn, Rd, Rm, readnum, writenum;
    reg [1:0] op, ALUop, shift;
    reg [4:0] imm5;
    reg [7:0] imm8;
    
//update decoder bit fields anytime output from instruction reg changes
always @(*) begin 
    opcode = ireg[15:13];
    op = ireg[12:11];
    ALUop = ireg[12:11];
    imm5 = ireg[4:0];
    imm8 = ireg[7:0];
    shift = ireg[4:3];
    Rn = ireg[10:8];
    Rd = ireg[7:5];
    Rm = ireg[2:0];
end

//sign extension for imm5, 5 bits -> 16 bits
always @(*) begin
    if(imm5[4] == 1'b0) begin 
        sximm5 = {11'b00000000000, imm5}; end //positive
    else begin
        sximm5 = {11'b11111111111, imm5}; end //negative
end

//sign extension for imm8, 8 bits -> 16 bits
always @(*) begin
    if(imm8[7] == 1'b0) begin
        sximm8 = {8'b00000000, imm8}; end //positive
    else begin
        sximm8 = {8'b11111111, imm8}; end //negative
end

//3 input (Rn, Rd, Rn) mux for writenum and readnum, based on 3 bit nsel
always @(*) begin
    case(nsel)
        3'b100 : begin readnum = Rn; writenum = Rn; end //Rn
        3'b010 : begin readnum = Rd; writenum = Rd; end //Rd
        3'b001 : begin readnum = Rm; writenum = Rm; end //Rm
        default : begin readnum = 3'bxxx; writenum = 3'bxxx; end
    endcase
end

endmodule