`define MNONE 2'b00
`define MREAD 2'b01
`define MWRITE 2'b10

module lab7_top(KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);
    input [3:0] KEY;
    input [9:0] SW;
    output [9:0] LEDR;
    output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

    wire [1:0] mem_cmd;
    wire [8:0] mem_addr;
    wire [15:0] dout, read_data, write_data;
    wire N, V, Z, eqwriteout, eqreadout, msel, enable, write;

cpu CPU(.clk(~KEY[0]), .reset(~KEY[1]), .read_data(read_data), .N(N), .V(V), .Z(Z), .write_data(write_data));

assign din = write_data;

equality #(2) eqwrite(`MWRITE, mem_cmd, eqwriteout);
equality #(2) eqread(`MREAD, mem_cmd, eqreadout); 
equality #(1) eqsel(1'b0, mem_addr[8:8], msel);

assign write = eqwriteout && msel;
assign enable = eqreadout && msel;

RAM #(16, 8, "data.txt") MEM(clk, mem_addr[7:0], mem_addr[7:0], 1'b0, write_data, dout); 

assign read_data = enable ? dout : {16{1'bz}};
endmodule

module RAM(clk, read_address, write_address, write, din, dout);

parameter data_width = 32;
parameter addr_width = 4;
parameter filename = "data.txt";

input clk;
input [addr_width-1:0] read_address, write_address;
input write;
input [data_width-1:0] din;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;

reg [data_width-1:0] mem [2**addr_width-1:0];

initial $readmemb(filename, mem);

always @ (posedge clk) begin
    if(write)
        mem[write_address] <= din; 
    dout <=mem[read_address];
end
endmodule

//2 input Mux
module Muxtop(in1, in2, sel, out);
    parameter k = 16;
    input [k-1:0] in1, in2;
    input sel;
    output reg [k-1:0] out;

    always @(*) begin
        case(sel) //determines use of new or old data
        1'b0 : out = in1;
        1'b1 : out = in2;
        default : out = {k{1'bx}};
        endcase
    end
endmodule

module equality(in1, in2, out);
    parameter k = 16;
    input [k-1:0] in1, in2;
    output reg out;

    always @(*) begin
        
        if(in1 == in2)
        out = 1'b1;
        else
        out = 1'b0;
    end
endmodule

module adder(in, out);
    parameter k = 8;

    input [k-1:0] in;
    output [k-1:0] out;

    assign out = in + {k{1'b1}};

endmodule