/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */

module regfile(data_in, writenum, write, readnum, clk, data_out );
    input [15:0] data_in;
    input [2:0] writenum, readnum;
    input write, clk;
    output [15:0] data_out;
    wire [15:0] R0, R1, R2, R3, R4, R5, R6, R7; 

    wire [7:0] anding;
    wire [7:0] anded;
    wire [7:0] select;

Dec #(3,8) D1(writenum, anding);

//assign anded = anding && write;

assign anded[0] = anding[0] && write;
assign anded[1] = anding[1] && write;
assign anded[2] = anding[2] && write;
assign anded[3] = anding[3] && write;
assign anded[4] = anding[4] && write;
assign anded[5] = anding[5] && write;
assign anded[6] = anding[6] && write;
assign anded[7] = anding[7] && write;

vDFFr #(16) F1(clk, data_in, anded[0], R0);
vDFFr #(16) F2(clk, data_in, anded[1], R1);
vDFFr #(16) F3(clk, data_in, anded[2], R2);
vDFFr #(16) F4(clk, data_in, anded[3], R3);
vDFFr #(16) F5(clk, data_in, anded[4], R4);
vDFFr #(16) F6(clk, data_in, anded[5], R5);
vDFFr #(16) F7(clk, data_in, anded[6], R6);
vDFFr #(16) F8(clk, data_in, anded[7], R7);

Dec #(3,8) D2(readnum, select);

Mux8 #(16) M1(R0, R1, R2, R3, R4, R5, R6, R7, select, data_out);

endmodule

module Dec(a, b);
    parameter n = 3;
    parameter m = 8;

    input [n-1:0] a;
    output [m-1:0] b;

    wire [m-1:0] b = 1 << a;
endmodule

module Mux8(R0, R1, R2, R3, R4, R5, R6, R7, select, data_out);
    parameter k = 16;
    input [k-1:0] R0, R1, R2, R3, R4, R5, R6, R7; 
    input [7:0] select;
    output [k-1:0] data_out;
    reg [k-1:0] data_out;

    always @(*) begin
        case(select)
        8'b00000001 : data_out = R0;
        8'b00000010 : data_out = R1;
        8'b00000100 : data_out = R2;
        8'b00001000 : data_out = R3;
        8'b00010000 : data_out = R4;
        8'b00100000 : data_out = R5;
        8'b01000000 : data_out = R6;
        8'b10000000 : data_out = R7;
        default: data_out = {8'bxxxxxxxx};
        endcase
    end
endmodule

module vDFFr (clk, in, anded, out);
    parameter k = 16;
    input clk, anded;
    input [k-1:0] in;
    output [k-1:0] out;
    reg [k-1:0] out;


    always @(posedge clk) begin
        if (anded == 1'b1) begin
            out = in; end
    end
endmodule