risc-processor-211 / CPEN Lab 7 / shifter.v
shifter.v
Raw
module shifter(in, shift, sout);
   
    //I/O for Shifter
    input [15:0] in;
    input [1:0] shift;
    output reg [15:0] sout;
    wire temp = in[15];

    always @(*) begin
        case(shift) //decides whether to not shift, shift left or right, or shift right with MSB maintained
        2'b00: sout = in;
        2'b01: sout = in << 1;
        2'b10: sout = in >> 1;
        2'b11: begin
                sout = in >> 1;
                sout[15] = temp; //assigns new MSB to inputted MSB
        end
        default: sout = {16{1'bX}};

        endcase
    end
endmodule