/* CPEN 211 Lab 7: Simple RISC Machine */
/* Prayetnaa Kansakar & Danial Jaber */
/* vDFFE.v */


//D flip flop with load enable
module vDFFE(clk, load, in, out);
    parameter n = 16;
    input clk, load;
    input [n-1:0] in;
    output reg [n-1:0] out;
    reg [n-1:0] next_out;

    always @(*) begin // load decides the output of vDFFE
    	if(load == 1'b1)
	next_out = in;
    	else
	next_out = out;
    end    

       always @(posedge clk) //updates DFF when clock is triggered
        out = next_out;
endmodule