EECS151 / fpga_labs_fa20 / lab3 / src / tone_generator.v
tone_generator.v
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`timescale 1ns/1ns

module tone_generator (
    input clk,
    input output_enable,
    input [23:0] tone_switch_period,
    input volume,
    output square_wave_out
);
    wire duty;
    reg [23:0] clk_counter = 0;
    reg wave = 0;

    assign duty = (volume) ? (clk_counter[0] == 0) : (clk_counter[8:0] == 0);
    assign square_wave_out = (output_enable && duty && (tone_switch_period != 24'd0)) ? wave : 1'b0;
   
    always @(posedge clk) begin
        if (clk_counter > tone_switch_period) begin
	    clk_counter <= 0;
            wave <= ~wave;
        end 
	    else begin
	        clk_counter <= clk_counter + 1;
        end
    end


endmodule