`timescale 1ns/1ns

module z1top (
    input CLK_125MHZ_FPGA,
    input [3:0] BUTTONS,
    input [1:0] SWITCHES,
    output [5:0] LEDS,
    output aud_pwm,
    output aud_sd
);
    assign aud_sd = SWITCHES[0];   
    tone_generator audio_controller (.clk(CLK_125MHZ_FPGA),
                                     .output_enable(aud_sd),
			 	                     .tone_switch_period({20'd0, BUTTONS[3:0]} << 16),
			 	                     .volume(SWITCHES[1]),
			 	                     .square_wave_out(aud_pwm)
				                    );
endmodule