module synchronizer #(parameter width = 1) (
    input [width-1:0] async_signal,
    input clk,
    output [width-1:0] sync_signal
);
    reg [width-1:0] mid = 0;
    reg [width-1:0] out = 0;

    assign sync_signal = out;
    always @(posedge clk) begin 
        mid <= async_signal;
        out <= mid;
    end
    
endmodule