module edge_detector #( parameter width = 1 )( input clk, input [width-1:0] signal_in, output [width-1:0] edge_detect_pulse ); reg [width-1:0] old_signal = 0; reg [width-1:0] pulse = 0; assign edge_detect_pulse = pulse; // Needed pulse reg to ensure width of edge detect was // exactly one clock cycle. Not sure if this is necessary // since our debouncer aligns signal_in with clk. (?) always @(posedge clk) begin old_signal <= signal_in; pulse <= (signal_in & ~old_signal); end endmodule