FPGA-RISC-V-CPU / hardware / build / impl / usage_statistics_webtalk.html
usage_statistics_webtalk.html
Raw 
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3247384</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Dec  9 08:08:13 2022</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2021.1 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>08ee37da3dbc4bca9f33ded9a04d64fa</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>8dedbe9220ec504db315f8139ef10657</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>8dedbe9220ec504db315f8139ef10657</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z020</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-3470T CPU @ 2.90GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>1699.727 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>CentOS</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>CentOS Linux release 7.9.2009 (Core)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=[unknown]</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=GateLvl</TD>
   <TD>export_simulation_activehdl=0</TD>
   <TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
   <TD>export_simulation_questa=0</TD>
   <TD>export_simulation_riviera=0</TD>
   <TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=0</TD>
   <TD>synthesisstrategy=[unknown]</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=1</TD>
   <TD>totalsynthesisruns=0</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=4</TD>
    <TD>carry4=104</TD>
    <TD>fdre=543</TD>
    <TD>fdse=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=14</TD>
    <TD>ibuf=4</TD>
    <TD>lut1=11</TD>
    <TD>lut2=128</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=185</TD>
    <TD>lut4=297</TD>
    <TD>lut5=269</TD>
    <TD>lut6=740</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf=3</TD>
    <TD>obuft=6</TD>
    <TD>plle2_adv=2</TD>
    <TD>ramb36e1=34</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32=126</TD>
    <TD>rams32=20</TD>
    <TD>vcc=13</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=4</TD>
    <TD>carry4=104</TD>
    <TD>fdre=543</TD>
    <TD>fdse=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=13</TD>
    <TD>ibuf=4</TD>
    <TD>lut1=11</TD>
    <TD>lut2=128</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=185</TD>
    <TD>lut4=297</TD>
    <TD>lut5=269</TD>
    <TD>lut6=740</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf=3</TD>
    <TD>obuft=6</TD>
    <TD>plle2_adv=2</TD>
    <TD>ram16x1d=29</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram32m=10</TD>
    <TD>ram32x1d=4</TD>
    <TD>ramb36e1=34</TD>
    <TD>vcc=13</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-aggressive_hold_fix=default::[not_specified]</TD>
    <TD>-bram_register_opt=default::[not_specified]</TD>
    <TD>-clock_opt=default::[not_specified]</TD>
    <TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-critical_pin_opt=default::[not_specified]</TD>
    <TD>-directive=default::[not_specified]</TD>
    <TD>-dsp_register_opt=default::[not_specified]</TD>
    <TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fanout_opt=default::[not_specified]</TD>
    <TD>-hold_fix=default::[not_specified]</TD>
    <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
    <TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-placement_opt=default::[not_specified]</TD>
    <TD>-restruct_opt=default::[not_specified]</TD>
    <TD>-retime=default::[not_specified]</TD>
    <TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-shift_register_opt=default::[not_specified]</TD>
    <TD>-uram_register_opt=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vhfn=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=68</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=545</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_design_analysis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-bounding_boxes=default::[not_specified]</TD>
    <TD>-cells=default::[not_specified]</TD>
    <TD>-complexity=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-congestion=default::[not_specified]</TD>
    <TD>-end_point_clocks=default::[not_specified]</TD>
    <TD>-extend=default::[not_specified]</TD>
    <TD>-extract_metrics=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-file=default::[not_specified]</TD>
    <TD>-full_logical_pin=default::[not_specified]</TD>
    <TD>-hierarchical_depth=default::[not_specified]</TD>
    <TD>-hold=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-logic_level_dist_paths=default::[not_specified]</TD>
    <TD>-logic_level_distribution=default::[not_specified]</TD>
    <TD>-logic_levels=default::[not_specified]</TD>
    <TD>-max_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_paths=default::[not_specified]</TD>
    <TD>-min_congestion_level=default::5</TD>
    <TD>-min_level=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_header=default::[not_specified]</TD>
    <TD>-of_timing_paths=default::[not_specified]</TD>
    <TD>-pploc_distance=default::[not_specified]</TD>
    <TD>-qor_summary=[specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-quiet=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-return_timing_paths=default::[not_specified]</TD>
    <TD>-routed_vs_estimated=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-routes=default::[not_specified]</TD>
    <TD>-setup=default::[not_specified]</TD>
    <TD>-show_all_congestion_windows=default::false</TD>
    <TD>-suggestion=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-timing=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>runtime=0.49 secs</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage_count</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>qor_summary=2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-max_msgs_per_check=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>plio-8=1</TD>
    <TD>zps7-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_prohibited=0</TD>
    <TD>bufgctrl_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufgctrl_util_percentage=6.25</TD>
    <TD>bufhce_available=72</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
    <TD>bufio_available=16</TD>
    <TD>bufio_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_prohibited=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
    <TD>bufmrce_available=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_prohibited=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=16</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_prohibited=0</TD>
    <TD>bufr_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_util_percentage=0.00</TD>
    <TD>mmcme2_adv_available=4</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
    <TD>plle2_adv_available=4</TD>
    <TD>plle2_adv_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_prohibited=0</TD>
    <TD>plle2_adv_used=1</TD>
    <TD>plle2_adv_util_percentage=25.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=220</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_prohibited=0</TD>
    <TD>dsps_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=140</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_prohibited=0</TD>
    <TD>block_ram_tile_used=34</TD>
</TR><TR ALIGN='LEFT'>    <TD>block_ram_tile_util_percentage=24.29</TD>
    <TD>ramb18_available=280</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
    <TD>ramb36_fifo_available=140</TD>
    <TD>ramb36_fifo_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_prohibited=0</TD>
    <TD>ramb36_fifo_used=34</TD>
    <TD>ramb36_fifo_util_percentage=24.29</TD>
    <TD>ramb36e1_only_used=34</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=2</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=104</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=543</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=4</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=128</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=185</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=297</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=269</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=740</TD>
    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=6</TD>
    <TD>plle2_adv_functional_category=Clock</TD>
    <TD>plle2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=34</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=124</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=21</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=26600</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_prohibited=0</TD>
    <TD>f7_muxes_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>f7_muxes_util_percentage=0.00</TD>
    <TD>f8_muxes_available=13300</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=73</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_prohibited=0</TD>
    <TD>lut_as_logic_used=1413</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_util_percentage=2.66</TD>
    <TD>lut_as_memory_available=17400</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=73</TD>
    <TD>lut_as_memory_util_percentage=0.42</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=106400</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_prohibited=0</TD>
    <TD>register_as_flip_flop_used=543</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_util_percentage=0.51</TD>
    <TD>register_as_latch_available=106400</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
    <TD>slice_luts_available=53200</TD>
    <TD>slice_luts_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_prohibited=0</TD>
    <TD>slice_luts_used=1486</TD>
    <TD>slice_luts_util_percentage=2.79</TD>
    <TD>slice_registers_available=106400</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_prohibited=0</TD>
    <TD>slice_registers_used=543</TD>
    <TD>slice_registers_util_percentage=0.51</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=73</TD>
    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_prohibited=0</TD>
    <TD>lut_as_logic_used=1413</TD>
    <TD>lut_as_logic_util_percentage=2.66</TD>
    <TD>lut_as_memory_available=17400</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_prohibited=0</TD>
    <TD>lut_as_memory_used=73</TD>
    <TD>lut_as_memory_util_percentage=0.42</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_available=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_prohibited=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=53</TD>
    <TD>lut_in_front_of_the_register_is_used_available=53</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=53</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_used_prohibited=53</TD>
    <TD>lut_in_front_of_the_register_is_used_used=168</TD>
    <TD>register_driven_from_outside_the_slice_fixed=168</TD>
    <TD>register_driven_from_outside_the_slice_used=221</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_within_the_slice_fixed=221</TD>
    <TD>register_driven_from_within_the_slice_used=322</TD>
    <TD>slice_available=13300</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_prohibited=0</TD>
    <TD>slice_registers_available=106400</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=543</TD>
    <TD>slice_registers_util_percentage=0.51</TD>
    <TD>slice_used=469</TD>
    <TD>slice_util_percentage=3.53</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=320</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=149</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=13300</TD>
    <TD>unique_control_sets_fixed=13300</TD>
    <TD>unique_control_sets_prohibited=0</TD>
    <TD>unique_control_sets_used=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_util_percentage=0.12</TD>
    <TD>using_o5_and_o6_available=0.12</TD>
    <TD>using_o5_and_o6_fixed=0.12</TD>
    <TD>using_o5_and_o6_prohibited=0.12</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=72</TD>
    <TD>using_o5_output_only_available=72</TD>
    <TD>using_o5_output_only_fixed=72</TD>
    <TD>using_o5_output_only_prohibited=72</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_output_only_used=1</TD>
    <TD>using_o6_output_only_available=1</TD>
    <TD>using_o6_output_only_fixed=1</TD>
    <TD>using_o6_output_only_prohibited=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_prohibited=0</TD>
    <TD>bscane2_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bscane2_util_percentage=0.00</TD>
    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_prohibited=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
    <TD>efuse_usr_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_prohibited=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_prohibited=0</TD>
    <TD>frame_ecce2_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_util_percentage=0.00</TD>
    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_prohibited=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_prohibited=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
    <TD>xadc_available=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_fixed=0</TD>
    <TD>xadc_prohibited=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
</BODY>
</HTML>
Powered by GitFront